1. Field of the Invention
The present invention relates to a semiconductor device having a gate electrode and an impurity diffusion layer different in conductivity type from each other, and a method of manufacturing the same semiconductor device, and in particular to semiconductor devices suitably used for a CMOS cell array in a memory LSI.
2. Description of the Prior Art
In an LSI (large scale integrated circuit), it is preferable that the resistances of electrodes and wiring are as low as possible, so that metallic material is suitable as the electrode and wiring material from the practical standpoint. In the case of a MOS transistor, in particular where a metallic layer is formed on an oxide film, however, since the atoms of the metal enter the oxide film or react with the oxide film, there exists a problem in that the breakdown voltage decreases or the interface level increases. Accordingly, poly-crystal silicon has been so far used, because the resistance thereof is not so high and can be further reduced by addition of impurities thereto.
In the case of the poly-crystal silicon, however, even if any impurities are added thereto, there exists a limit of the resistance to be lowered. Accordingly, with the advance of the further microminiaturization and the higher operation speed of the MOS transistor, the above-mentioned resistances of the electrodes and the wiring have raised a new problem more and more in the field of the LSI. Therefore, finally a realization of an electrode wiring material lower in resistance than the poly-crystal silicon has been required.
For satisfying this need, recently, there has been developed a high men, ting point metal, which can be easily replaced with the poly-crystal silicon because the specific resistance thereof is lower by one figure (cipher) than that of the poly-crystal silicon and further the characteristics thereof are similar to those of the poly-crystal silicon. The above-mentioned high melting point metal is used as the electrode and wiring material for the CMOS transistor, in the form of a two-layer lamination structure of this metal layer (or a siliside layer containing this metal) and a poly-crystal silicon layer. In particular, a combination of the high melting point metal siliside and the poly-crystal silicon layer has been well known under the name of "polyside".
When the high melting point metal or the siliside layer is formed on an oxide film via the poly-crystal silicon layer, it is possible to reduce the resistance of the material containing metal and further to eliminate the above-mentioned problems with respect to the metal atoms.
On the other hand, in the LSI, in particular in the case of the memory cell which is microminiaturized more and more, it is effective that the gate electrodes are used as the wiring layer as they are and additionally can be connected directly to the diffusion layer in order to improve the integration rate (density).
The conventional process of manufacturing an ohmic contact portion between the polyside gate and the diffusion layer in the SRAM (static random access memory) LSI memory cell array will be described hereinbelow with reference to FIGS. 1A to 1D.
First, as shown in FIG. 1A, a field oxide film 302 is formed on a P-type semiconductor substrate 301 in accordance with a selective oxidization method. Further, a gate oxide film 303 with a film thickness of about 150 .ANG. is formed, and further a poly-crystal silicon layer 304 with a film thickness of about 500 to 1000 .ANG. is deposited on the gate oxide film 303 as the gate electrode wiring material.
Secondly, as shown in FIG. 1B, a contact hole 305 is formed by removing the gate oxide film 303 and the poly-crystal silicon layer 304, on which an ohmic contact portion between the gate electrode and the diffusion layer is to be formed, in accordance with lithographic technique and etching technique. Successively, a poly-crystal silicon layer 306 with a film thickness of about 500 to 1000 .ANG. is deposited all over the surface of the substrate 301 in the same way as with the case of the polyp-crystal silicon layer 304.
Thereafter, as shown in FIG. 1C, an N-type impurity is added to the poly-crystal silicon layer 304 and the poly-crystal silicon layer 306 in accordance with P diffusion technique or ion implantation technique and annealing, and simultaneously an N-type diffusion layer 307 is formed on the surface region corresponding to the contact hole 305 of the substrate 301.
Further, as shown in FIG. 1D, a high melting point metal siliside layer 308 with a film thickness of about 1000 .ANG. is formed on the poly-crystal silicon layer 306 by sputtering tungsten siliside. The presence of this siliside layer 308 serves to reduce the resistance of the gate wiring.
In the above-mentioned conventional process of manufacturing the semiconductor device as described above, when the ohmic contact is formed between the wiring formed by a lamination layer (composed of the impurity-added poly-crystal silicon layer 306 and the siliside layer 308) or the gate electrode of the MOSFET and the diffusion layer 307 formed on the silicon substrate 301, the conductivity type of the polyside layer 308 and the diffusion layer 307 must be the same as each other (N-type in the case of FIGS. 1C and D).
That is, in the case of the gate electrode to which an N-type impurity is added, the diffusion layer contacting the gate electrode to which the N-type impurity is added must be the same N conductivity type. In the same way, in the case of the gate electrode to which a P-type impurity is added, the diffusion layer contacting the gate electrode to which the P-type impurity is added must be the same P conductivity type.
Therefore, in a CMOS circuit of the SRAM memory cell, when the gate electrode is required to be connected to the impurity diffusion layer of different conductivity type, it has been so far necessary to use another metallic wire (e.g., Al) other than the polyside or to form the N-type region and the P-type region separately from each other by implanting ions into the polyside wiring. In the case where Al wiring is used, however, there exist problems in that the device element cannot be microminiaturized and further the number of manufacturing steps increases, thus resulting in a higher cost. In the case where two regions of different conductivity types are formed by ion implantation, however, there exists another problem in that since the conductivity type of the gate electrode is closely related to the threshold voltage of the MOSFET, the conductivity type cannot be easily determined under consideration of only the gate electrode and the diffusion layer, in addition to the problems with an increase of the number of manufacturing steps due to ion implantation and with a higher cost.